Senior Memory Controller RTL Design Engineer
Core
Define and implement micro-architectural specifications for high-performance DDR4/DDR5 memory controllers in Verilog/System Verilog, optimizing for area, power, and performance within SoC environments.
Role type
Senior IC RTL Design Engineer (Memory Controller)
Builds
Functional memory controller IP blocks integrated into System-on-Chip (SoC) designs.
Domain
Semiconductor hardware design, high-speed digital logic, memory subsystems.
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Verilog/System Verilog coding, high-speed design principles, low power design principles, multi-bit error correction (Reed-Solomon), industry standard interface protocols (CHI, APB, AMBA), front-end verification tools, synthesis and static timing analysis (STA), scripting (Perl, Tcl, Python), SoC development experience.
Preferred skills
Experience with AI/automation for design tasks, collaboration with IP providers.
Technologies
Verilog, System Verilog, Perl, Tcl, Python, CHI, APB, AMBA, Reed-Solomon, DDR4, DDR5.
Responsibilities
Define and implement micro-architectural specifications, refine implementations for area/power/performance, integrate functional IP into SoC, write basic tests for functionality, perform design quality checks (Lint, CDC/RDC, Low Power Intent, timing QoR), automate tasks using scripting.
Seniority
Senior, hands-on IC
