Staff Engineer, ASIC STA
Core
Staff Engineer leading Static Timing Analysis (STA), Synthesis, and Logic Equivalence Checking (LEC) for complex mixed-signal ASIC designs in memory and storage solutions.
Role type
Staff Engineer, ASIC STA
Builds
High-frequency, multi-GHz silicon builds for memory and storage products
Domain
Semiconductor / ASIC Design / Memory & Storage
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Static Timing Analysis (STA), Synthesis, Logic Equivalence Checking (LEC), mixed-signal IP integration, timing model development, hierarchical design management, high-frequency clock handling, scripting and automation, EDA tools, low-power design, critical path analysis
Preferred skills
AI and AI-enabled workflows
Technologies
EDA tools, scripting languages
Responsibilities
Manage synthesis to timing closure ensuring silicon success, develop constraints and timing models, identify and meet requirements for critical paths in multi-GHz builds, integrate new mixed signal complex IPs
Seniority
Staff, hands-on IC
