SoC Physical Design Senior Manager, HBM
Core
Lead a team of physical design and verification engineers to implement advanced HBM SoC logic/base die designs from netlist to GDSII, ensuring best-in-class PPA and robust signoff for tapeout.
Role type
Senior IC SoC Physical Design Manager (HBM)
Builds
Heterogeneous Integration Group (HIG) HBM SoC products
Domain
Semiconductor / Memory / SoC Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SoC physical design implementation (netlist to GDSII), advanced node design, EDA tool proficiency (Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre), STA fundamentals, clocking and constraints, power intent (UPF/CPF), physical verification (DRC/LVS/ERC), hierarchical design integration, IR/EM analysis, tapeout execution, AI/LLM workflow development
Preferred skills
HBM/DRAM adjacent SoC design experience, mentoring junior engineers
Technologies
Cadence Innovus, Synopsys ICC2, Synopsys PrimeTime, Siemens Calibre, UPF, CPF, SDC
Responsibilities
Recruit and mentor physical design teams; plan project resourcing and timelines; drive floorplanning, placement, CTS, routing, and optimization; manage timing closure across multi-mode/multi-corner scenarios; integrate complex IP (controllers, NOC, PHY-adjacent logic); coordinate physical signoff (DRC/LVS/IR drop); support tapeout and post-silicon debug; develop AI-driven design workflows
Seniority
Senior, hands-on IC with team leadership
