Senior Layout Designer
Core
Designing high-quality analog and mixed-signal layouts for critical blocks including sensors, PLLs, ADCs, and digital arrays.
Role type
Senior IC analog layout engineer
Builds
Memory and storage solutions (DRAM, NAND, NOR) for data centers, AI, 5G, and mobile applications
Domain
Semiconductor manufacturing / Analog and Digital IC design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Cadence VXL proficiency, LVS/DRC debugging, analog layout fundamentals (matching, EM, latch-up), floor-planning, placement, routing, ECO/LCO/DFM execution, circuit performance analysis (speed, capacitance, power, area)
Preferred skills
AI tool proficiency for automation
Technologies
Cadence VXL
Responsibilities
Implement high-quality layouts within design constraints, oversee layout process from floor-planning to routing, coordinate with design and verification teams, execute secondary layout tasks like ECO and DFM, deliver mid-size blocks in Core/Pitch and periphery areas
Seniority
Senior, hands-on IC
