Principal Engineer HBM Design Verification
Core
Lead verification architecture and methodology for next-generation HBM designs, ensuring robust sign-off strategies and workflow efficiency.
Role type
Principal IC design verification engineer (HBM)
Builds
Next-generation HBM memory chips
Domain
Semiconductor / Memory / HBM
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, Formal Verification, SoC architecture, bus protocols (AXI, PCIe), simulation, coverage analysis, regression management, team leadership
Preferred skills
Pre-Silicon Verification, DDR/GDDR/LPDDR memory verification, SerDes PHY IP verification, Python/TCL scripting, AI tool usage (Copilot/Claude)
Technologies
UVM, Formal Verification tools, SystemVerilog, AXI, PCIe
Responsibilities
Define verification architecture and methodology; Develop verification plans, coverage strategies, and sign-off criteria; Architect and implement UVM-based testbenches; Apply Formal Verification techniques; Mentor verification engineers on advanced methodologies
Seniority
Principal, hands-on IC with mentorship
