Design Verification Manager
Core
Lead a world-class silicon verification team to architect, guide, and execute advanced verification strategies for high-performance, next-generation semiconductor products, ensuring zero-bug tape-outs.
Role type
Senior IC Design Verification Manager (Silicon/SoC)
Builds
Pre-silicon ASIC/SoC chips and IP blocks
Domain
Semiconductor / Hardware Design Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM methodology, Formal Verification, Emulation platforms (Palladium, Zebu, Veloce), Testbench architecture, Resource allocation, Cross-functional collaboration, Team leadership, Microarchitecture analysis
Preferred skills
AI/ML in verification pipelines, Multi-protocol high-speed interfaces (PCIe Gen6/7, CXL, HBM3, NVLink), Global team management
Technologies
SystemVerilog, UVM, Palladium, Zebu, Veloce
Responsibilities
Manage and mentor high-performing design verification engineers; Define global verification strategies and testbench architecture; Drive standard-setting execution using industry-best paradigms; Align with Architecture, RTL Design, and Physical Design teams to debug system-level failures; Allocate resources across multiple parallel chip/block schedules.
Seniority
Manager, hands-on technical authority with leadership
