SR ENGINEER, DDEG Design Methodology
Core
Own verification and end-to-end analysis of sophisticated full-chip gate-level custom designs for advanced low-power and power management technologies in DDR4, LPDDR4, DDR5, and LPDDR5 operating at up to 6400MT/s.
Role type
Senior IC verification engineer (DRAM memory)
Builds
Production verification environments and testbenches for high-speed DRAM and emerging memory architectures
Domain
Semiconductor memory (DRAM) and digital/mixed-signal verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, SPICE, gate-level circuit analysis, simulation and regression analysis, mixed-signal verification, Perl/Python scripting
Preferred skills
Real Number Models, AI-based tool validation, agentic workflows, previous DRAM memory field experience
Technologies
Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, Hspice
Responsibilities
Accelerate verification cycle time using AI-based tools and automation frameworks; Develop and maintain testbenches and test vectors for block and full-chip level designs; Validate AI outputs against specs, simulations, and coverage reports before design decisions; Collaborate globally on developing new verification flows and methodologies; Guide new team members and energetic engineers
Seniority
Senior, hands-on IC
