Senior Validation Engineer
Core
Validating DDR memory interfaces on complex SoC platforms, executing test plans, and debugging silicon issues to ensure memory subsystem functionality.
Role type
Senior IC validation engineer (memory subsystems)
Builds
Pre-silicon and post-silicon DDR memory platforms
Domain
Semiconductor hardware validation, memory subsystems
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DDR4/5/LPDDR5/6 protocols, memory controller architecture, DDR PHY architecture, silicon bring-up, firmware development/debug, C/Python scripting, signal integrity basics, test case creation, regression testing, stress testing, root cause analysis
Preferred skills
Experience with JTAG debuggers, oscilloscopes, logic analyzers, protocol analyzers, low-level embedded software validation, system stress validation, automation infrastructure
Technologies
DDR4, DDR5, LPDDR5, LPDDR6, C, Python, Perl, Shell scripting, JTAG, oscilloscopes, logic analyzers, protocol analyzers
Responsibilities
Perform functional validation of DDR memory subsystems on pre-silicon and post-silicon platforms; Execute validation test plans for DDR4, DDR5, LPDDR5, and LPDDR6 interfaces; Develop, enhance, and maintain validation test cases for memory controller, DDR PHY, training flows, initialization sequences, low-power features, and system-level stress scenarios; Support silicon bring-up activities, including DDR initialization, boot flow debug, memory training debug, and platform stabilization; Debug silicon issues related to DDR functionality, timing, training failures, memory errors, system hangs, boot failures, and performance anomalies; Develop and debug firmware used for DDR initialization, training, configuration, and validation; Analyze validation failures using logs, traces, register dumps, firmware debug messages, protocol analyzer outputs, oscilloscopes, logic analyzers, and other debug tools; Validate memory controller and PHY features across different operating frequencies, voltage corners, power states, and stress conditions; Create and maintain validation documentation, including test plans, test case specifications, debug notes, issue reports, and execution summaries; Participate in reviews of DDR architecture, controller features, PHY behavior, firmware flows, and validation coverage; Execute system stress scenarios involving memory bandwidth, concurrency, thermal stress, voltage/frequency scaling, low-power entry/exit, and long-duration stability testing; Collaborate with cross-functional teams to improve validation coverage, debug methodology, and automation infrastructure; Track validation progress, report issues clearly, and support defect triage through bug tracking systems
Seniority
Senior, hands-on IC
