MTS-RTL Verification Engineer
Core
Architect and develop scalable, reusable SystemVerilog/UVM verification environments for high-speed digital designs in advanced process nodes.
Role type
Senior IC RTL Verification Engineer
Builds
Verification environments and closure metrics for memory and storage solutions
Domain
Semiconductor / High-speed digital design
Required skills
SystemVerilog, UVM, Constrained-random testing, Formal Verification, Clock/reset/FSM/CDC fundamentals, High-speed digital design verification, Simulation/coverage/debug tools, Python/Perl/Tcl scripting
Preferred skills
Power-aware verification, High-speed memory subsystems, Global cross-site team collaboration
Technologies
SystemVerilog, UVM, Python, Perl, Tcl
Responsibilities
Own verification strategy and planning, Architect and develop scalable verification environments, Drive functional and code coverage closure, Lead debug and issue resolution, Provide verification status and risk assessment, Ensure verification readiness for high-speed operation, Improve verification methodologies and automation, Mentor engineers
Seniority
Senior, hands-on IC
