Senior ASIC Design Verification Engineer
Core
Developing advanced verification components for sophisticated System-on-Chip (SoC) designs and ensuring high-quality delivery for next-generation memory products.
Role type
Senior IC ASIC Design Verification Engineer
Builds
Production verification environments and testbenches for memory and storage SoCs
Domain
Semiconductor / Memory and Storage / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM methodologies, SystemVerilog, Python, constrained-random verification, functional coverage closure, SoC verification, IP verification, simulation environment development, complex debugging
Preferred skills
mixed-signal verification, DRAM protocol knowledge (DDR/LPDDR/GDDR), AI-assisted verification tools, AI/ML techniques for verification flows
Technologies
UVM, SystemVerilog, Python, AI-assisted verification tools
Responsibilities
Develop and maintain UVM-based SystemVerilog verification environments; Build and enhance Python-based testbenches and simulation infrastructure; Define and execute block and system-level verification plans; Debug complex functional and integration issues; Drive coverage closure and improve verification quality metrics; Explore and adopt AI-assisted techniques to improve verification productivity
Seniority
Senior, hands-on IC
