STAFF ENGINEER, DDEG Design Methodology
Core
Lead verification and end-to-end analysis for sophisticated full-chip gate-level custom designs in advanced low-power and power management technologies (DDR4, LPDDR4, DDR5, LPDDR5) operating at high speeds up to 6400MT/s.
Role type
Staff Engineer, Design Methodology (Verification)
Builds
Production verification environments, test benches, and test vectors for DRAM and emerging memory architectures.
Domain
Semiconductor / Memory / Digital & Mixed-Signal Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, SPICE, gate-level circuit analysis, simulation debugging, test case development, regression analysis, Perl/Python scripting
Preferred skills
Real Number Models, AI-based tool validation, agentic workflows, DRAM/SRAM domain expertise, AMS verification
Technologies
Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, Hspice
Responsibilities
Accelerate verification cycle time using AI tools and automation; validate AI outputs against specs and simulations; develop and maintain SV/UVM testbenches at block and full-chip levels; guide new team members; analyze complex CMOS designs.
Seniority
Staff, hands-on IC with mentorship
