Staff Engineer, Design Verification
Core
End-to-end verification execution for complex digital IP and subsystems within System-on-Chip (SoC) designs, ensuring first-pass silicon success through metric-driven verification and AI-assisted techniques.
Role type
Staff Engineer, IP Design Verification
Builds
Reusable IP blocks and subsystems for next-generation microcontrollers and microprocessors
Domain
Semiconductor / SoC Design / Digital Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> product features (verification environments, checkers, testbenches)
Required skills
UVM-based testbench architecture, SystemVerilog, assertions (SVA), constraint random verification, directed test methodologies, coverage closure, EDA toolkits, post-silicon debugging
Preferred skills
AI/ML-based verification tools, Python/Perl/TCL scripting, formal verification, high-speed IP knowledge
Technologies
UVM, SystemVerilog, SVA, EDA tools, Python, Perl, TCL
Responsibilities
Define and drive IP-level verification strategies including test plans and coverage models; Develop scalable, reusable UVM-based verification environments; Lead functional, code, assertion, and cross-coverage closure; Apply AI/ML-assisted techniques to accelerate coverage convergence; Drive constraint random and directed test methodologies; Collaborate with RTL, Architecture, and Emulation teams; Develop advanced checkers, scoreboards, and protocol monitors; Mentor junior engineers; Support Gate-Level Simulation and post-silicon debug.
Seniority
Staff, hands-on IC with mentorship
