PRINCIPAL ENGINEER, DDEG DESIGN METHOD
Core
Lead verification and end-to-end analysis for sophisticated full-chip gate-level custom designs in advanced low-power and power management technologies (DDR4, LPDDR4, DDR5, LPDDR5) operating at high speeds up to 6400MT/s.
Role type
Principal Engineer, DDEG Design Method
Builds
High-speed DRAM and emerging memory products
Domain
Semiconductor / Memory / Digital & Mixed-Signal Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, SPICE, gate-level circuit design analysis, simulation and debugging, test bench development, regression analysis, AI tool validation, mixed-signal verification
Preferred skills
PLI coding, Real Number Models, Perl/Python scripting, DRAM/SRAM domain experience, AMS verification and co-simulation
Technologies
Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, Hspice
Responsibilities
Accelerate verification cycle time using AI-based tools and automation frameworks; validate AI outputs against specs and simulations before design decisions; develop test cases and stimulus to increase functional coverage for DRAM architectures; build and maintain SV testbenches at block and full-chip levels; guide new team members and energetic engineers; participate in developing verification methodology and environments.
Seniority
Principal, hands-on IC with mentorship
