Principal Analog and Reliability Verification Engineer
Core
Developing verification solutions and methodologies for DRAM analog and reliability testing to ensure high-quality, reliable silicon.
Role type
Principal Analog and Reliability Verification Engineer
Builds
DRAM verification strategies, Python-based testbenches, and scalable verification flows
Domain
Semiconductor / Memory / Analog Circuit Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog simulation and debug, VLSI circuit design fundamentals, Reliability fundamentals (BTI, HCI, EM, TDDB), Python programming (OOP, advanced libraries), DRAM circuit design and system architecture
Preferred skills
Digital verification methodologies (SystemVerilog, UVM), Multi-layered multithreaded system design, AI-enabled process improvements
Technologies
Python, SystemVerilog, UVM, Circuit simulation tools, Waveform analysis tools
Responsibilities
Define and drive DRAM analog and reliability verification strategy including AI-enabled methodologies; Partner with design teams to standardize and improve verification methodologies; Develop and maintain Python-based verification testbenches and flows; Translate reliability requirements into actionable verification plans; Provide technical leadership by setting priorities, mentoring engineers, and driving innovation
Seniority
Principal, technical leadership & mentorship