Digital Physical Implementation and Integration Engineer
Core
Design and analyze digital and analog circuits for memory products, owning physical implementation and top-level integration of large digital designs in NAND products.
Role type
Senior IC digital physical design engineer (memory)
Builds
NAND memory chips and silicon-to-systems solutions
Domain
Semiconductor / Memory / Digital Physical Design
Deliverable
production ML models | product features
Required skills
Digital physical design, Static timing analysis (STA), Floorplanning, Placement, Routing, Synthesis, Physical verification (DRC/LVS), Tcl/Python automation, CMOS logic, Standard cells, EM/IR analysis
Preferred skills
Master's/Ph.D. in EE/CE, Multi-partition SoC integration, Clock planning, DFT/scan compression, EDA-vendor AI tools
Technologies
Cadence Innovus, Synopsys ICC2/Design Compiler, Calibre, PrimeTime, Tcl, Python, Linux/Unix, Git
Responsibilities
Drive blocks and full-chip partitions through synthesis handoff, floorplan, place-and-route, and timing/DRC/LVS closure; Perform hierarchical design planning and top-level assembly; Automate flows in Tcl/Python; Partner with STA, DFT, CAD, and custom-layout teams
Seniority
Senior, hands-on IC
