Senior Design Engineer : Custom Digital Hard Macros (Physical IP)
Core
Design and implementation of custom and semi-custom digital hard macros for Arm CPU, GPU, NPU, and SoC products, covering power delivery, clocking, and asynchronous interfaces.
Role type
Senior IC physical design engineer (hard macros)
Builds
Custom digital hard macros and physical IP blocks
Domain
Semiconductor / Digital Physical Design
Required skills
RTL design, synthesis, floorplanning, place-and-route, static timing analysis, physical verification, Verilog/SystemVerilog, Tcl/Python scripting, timing constraints, CDC concepts, transistor-level concepts, Liberty models
Preferred skills
Hard-macro IP development, advanced process nodes, low-power design, asynchronous interfaces, silicon validation
Technologies
Cadence Innovus, Tempus, Genus
Responsibilities
Develop RTL, timing constraints, and automation flows; Execute synthesis, floorplanning, place-and-route, and signoff; Analyze and debug timing, power, congestion, and DRC/LVS issues; Collaborate with AMS, verification, and SoC integration teams; Support silicon validation and correlation.
Seniority
Mid-Senior, hands-on IC
