HBM LAYOUT ENGINEER
Core
Perform physical layout design of leaf cells, standard cells, and sub-blocks for High Bandwidth Memory (HBM) products supporting AI and high-performance computing.
Role type
IC Layout Design Engineer
Builds
HBM memory chips for AI and high-performance computing applications
Domain
Semiconductor / Memory / VLSI
Deliverable
production ML models | product features
Required skills
VLSI design, circuit simulation, DRC/LVS verification, EDA tools (Cadence Virtuoso, Mentor Calibre), Python/C++ scripting, analog layout concepts
Preferred skills
pre-silicon development, custom layout, CMOS fundamentals, semiconductor fabrication processes, layout impact analysis (speed, capacitance, power, area)
Responsibilities
Perform physical layout design of leaf cells, standard cells, and sub-blocks; Implement and interpret physical verification checks including DRC, LVS, and related validation activities; Apply AI-driven methodologies to automate engineering processes
Seniority
Mid-level, hands-on IC engineer
