Staff Design Engineer, HBM Architecture
Core
Architect, design, and optimize high-speed datapath circuitry for next-generation High Bandwidth Memory (HBM) products, focusing on logic-die and core-die architectures to enable industry-leading bandwidth, power efficiency, and reliability.
Role type
Staff IC Digital Design Architect (HBM Datapath)
Builds
Next-generation High Bandwidth Memory (HBM) products
Domain
Semiconductor / Memory / High-Speed Digital Design
Required skills
High-speed digital datapath design, Digital schematic build, RTL design, Mixed-signal datapath implementation, HBM/DRAM architecture knowledge, Static timing analysis (STA), Timing closure methodologies, Signal integrity control, Power optimization, Advanced process-node challenges
Preferred skills
Layout and floorplanning for high-speed datapath, Multi-channel HBM operation, Lane redundancy and remapping mechanisms
Technologies
RTL, Schematic, AI-enabled tools (Microsoft Copilot)
Responsibilities
Architect and design HBM read/write datapath across core and logic die, Develop high-speed low-latency datapath circuits supporting multi-channel HBM architectures, Optimize datapath designs for bandwidth, power, area, and timing closure, Design and integrate data reliability features including parity and ECC hooks, Collaborate with multi-functional teams to translate specifications into robust micro-architectures, Contribute to design reviews, documentation, and technical mentoring
Seniority
Staff, hands-on IC with mentorship
