RTL Design Engineer, Networking / NoC
Core
Design and implement high-performance RTL for next-generation AI accelerator silicon, translating system requirements into efficient hardware microarchitectures.
Role type
Senior IC RTL Design Engineer (AI Accelerator / NoC)
Builds
AI-native silicon and tightly integrated systems for frontier AI models
Domain
Semiconductor / AI Hardware / High-Performance Computing
Deliverable
production ML models
Required skills
ASIC RTL design, SystemVerilog, Verilog, microarchitecture development, hardware/software co-design, synthesis, timing closure, physical design optimization, Network-on-Chip (NoC), interconnect architectures, high-bandwidth data movement
Preferred skills
AI accelerator design, high-performance computing, hardware/software co-design
Technologies
SystemVerilog, Verilog
Responsibilities
Design and implement high-performance RTL for AI accelerator silicon; Collaborate with architecture and software teams to translate system-level requirements into efficient hardware microarchitectures; Drive hardware/software co-design efforts to optimize performance, power, area, and scalability; Develop and optimize RTL for complex datapaths, control logic, interconnects, and other critical silicon subsystems; Evaluate architectural and microarchitectural tradeoffs across bandwidth, latency, throughput, and resource utilization; Partner with design verification and formal verification teams to ensure functional correctness and debug complex design issues
Seniority
Senior, hands-on IC
