MTS Design Engineer, Bonding and Packaging
Core
Drive electrical, thermal, and thermo-mechanical design and characterization of next-generation semiconductor packages (HBM, W2W, COW, Flip Chip, TSV) while integrating AI/ML tools to accelerate simulations and enable data-driven decision-making.
Role type
Senior IC design engineer (advanced packaging & AI integration)
Builds
Production-ready advanced packaging technologies and heterogeneous integration solutions for AI-era memory and storage
Domain
Semiconductor industry / Advanced Packaging / AI-enabled Engineering
Deliverable
production ML models | product features
Required skills
Semiconductor packaging design (HBM, W2W, COW, Flip Chip, TSV), multiphysics simulation (electrical, thermal, thermo-mechanical), AI/ML and generative AI tool integration, Design of Experiments (DOE), statistical analysis, Chip-Package Interactions (CPI) modeling, vendor and testing lab collaboration
Preferred skills
Signal Integrity analysis, high-speed package design, Cadence layout tools, data acquisition, numerical analysis (MATLAB, Excel, JMP)
Technologies
JMP, MATLAB, Excel, Cadence, generative AI, predictive analytics
Responsibilities
Drive design advancements by capturing multiphysics mechanisms in simulation; propose thermal improvement solutions and roadmap alignment; validate mechanical and thermo-mechanical stress/strain structural models; design and implement testing procedures for material characterization; integrate AI workflows into package design and technology evaluations
Seniority
Senior, hands-on IC
