Advanced Packaging Power Delivery Senior
Core
Designing power-delivery architecture and advanced packaging for next-generation AI accelerators, spanning on-die grids to package/PCB levels.
Role type
Senior IC analog/power delivery and packaging engineer
Builds
Custom AI accelerator chips and multi-chiplet 3D-integrated systems
Domain
Semiconductor hardware design, AI accelerators, advanced packaging
Deliverable
production ML models
Required skills
on-die power grid design, package/PCB PDN analysis, 2.5D/3D IC packaging, multi-chiplet integration, interposer/substrate co-design, SI/PI verification, EDA tools for power integrity
Preferred skills
thermal modeling, co-simulation, AI accelerator custom ASIC flows, OSAT/vendor collaboration
Technologies
EDA tools for power integrity and PDN simulation
Responsibilities
Own end-to-end power-delivery design from on-die to PCB; lead advanced packaging architecture for 2.5D/3D stacking; perform SI/PI verification and sign-off; collaborate with Silicon Engineering and AIIS teams; develop power-delivery methodology and design guidelines; mentor team members; engage with external substrate and OSAT partners
Seniority
Senior, hands-on IC
