Senior Engineer- DEG Layout
Core
Design and develop critical analog, mixed-signal, and custom digital blocks at full chip level, including layout verification and automation.
Role type
Senior IC analog/mixed-signal layout engineer
Builds
Custom digital blocks, analog/mixed-signal circuits (PLL, ADC, DAC, LDO, etc.), and full chip layouts
Domain
Semiconductor manufacturing (memory and storage solutions)
Required skills
Analog layout design, Mixed-signal layout, Custom digital block layout, LVS/DRC verification, Antenna/Shield/Matching checks, EM/IR/Totem analysis, Auto placement and routing, Skill coding and automation, AI tool integration for layout reduction, Tape-out support
Preferred skills
Leadership in planning and delegation, Project management, Global team collaboration
Technologies
Cadence VLE/VXL, Mentor Calibre DRC/LVS
Responsibilities
Perform layout verification (LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem), develop digital block layouts using auto placement and route tools, guide team members in sub-block-level layouts, reduce layout effort using AI tools, deliver block-level layouts on time
Seniority
Senior, hands-on IC
