Senior Engineer- DEG Layout
Core
Design and develop analog, mixed-signal, and custom digital block layouts at full chip level for memory and storage solutions.
Role type
Senior IC physical design engineer (analog/mixed-signal)
Builds
Custom analog blocks (PLL, ADC, DAC, LDO, Bandgap, etc.) and full chip layouts
Domain
Semiconductor manufacturing / Analog IC design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog layout design, Mixed-signal layout, Custom digital block layout, LVS/DRC verification, Auto placement and routing, Skill coding and automation, Project planning and scheduling, Team leadership and mentoring, Physical verification, Tape-out support
Preferred skills
AI tool integration for layout effort reduction
Technologies
Cadence VLE/VXL, Mentor Graphic Calibre
Responsibilities
Perform layout verification (LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem), develop digital block layouts using auto tools, guide team members on sub-block layouts, communicate with global engineering teams, reduce layout effort using AI tools
Seniority
Senior, hands-on IC