Senior layout Engineer – DPG Layout
Core
Implement design and physical implementation of analog, mixed-signal, and custom digital blocks, supporting full-chip integration and verification.
Role type
Senior IC layout engineer (analog/mixed-signal)
Builds
Custom analog and mixed-signal blocks (sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, charge pumps) for memory and storage products
Domain
Semiconductor manufacturing, advanced CMOS process, memory (DRAM, SRAM, CAM, OTP)
Deliverable
production ML models | product features
Required skills
Analog layout fundamentals (matching, symmetry, electromigration, latch-up, IR-drop, coupling, crosstalk, parasitics), Cadence Virtuoso (VLE/VXL), Calibre DRC/LVS, AI-driven automation for layout scripts (SKILL/Python/TCL), ECO integration, yield and quality analysis
Preferred skills
Memory layout environment experience, mentoring junior engineers
Technologies
Cadence Virtuoso, Calibre, SKILL, Python, TCL
Responsibilities
Own block-level layout execution with focus on quality and turnaround time; perform DRC, LVS, antenna, yield, and quality checks; use AI tools to automate repetitive tasks; support custom/digital layout integration; collaborate with design and verification teams; review sub-block layouts from developing engineers
Seniority
Senior, hands-on IC
