Senior layout Engineer – DPG Layout
Core
Own the development and physical implementation of critical analog, mixed-signal, and custom digital blocks, including block-level and full-chip layout ownership.
Role type
Senior IC layout engineer (analog/mixed-signal/memory)
Builds
Analog, mixed-signal, and custom digital blocks for memory and storage solutions
Domain
Semiconductor manufacturing (VLSI/IC design)
Deliverable
production ML models
Required skills
Analog layout fundamentals, Cadence Virtuoso, Calibre DRC/LVS, AI-driven automation, memory layout (DRAM/SRAM/CAM/OTP), parasitic effects management, yield optimization, SKILL/Python/TCL scripting
Preferred skills
Experience with AI-assisted workflows, agentic AI flows, rule-aware automation, mentorship of engineers
Technologies
Cadence Virtuoso (VLE/VXL), Calibre, SKILL, Python, TCL
Responsibilities
Lead layout implementation using AI-assisted and automated workflows, perform and automate layout verification activities (DRC, LVS, Antenna, Yield, ESD, TOTEM, EM/IR), drive on-time delivery of blocks with risk prediction, develop AI-enabled methodologies for floorplanning and parasitic estimation, guide and mentor engineers in analog layout and automation-first approaches, collaborate with Design, CAD, Verification, and Program Management teams
Seniority
Senior, hands-on IC