Senior Engineer, IPDev Layout
Core
Design and development of critical analog, mixed-signal, custom digital blocks, and full chip level integration for advanced DRAM chips.
Role type
Senior IC Layout Design Engineer (Analog/Mixed-Signal)
Builds
Analog and mixed-signal IPs for DRAM, AI, and high-performance computing solutions
Domain
Semiconductor / Memory / VLSI
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog layout design, Custom digital block layout, LVS/DRC/Antenna verification, Cadence VLE/VXL, Mentor Calibre DRC/LVS, CMOS process knowledge (Planar/FinFET), Circuit-aware layout (speed/capacitance/power/area), Memory design hierarchy
Preferred skills
Temperature sensor/PLL/ADC/DAC/LDO design, Multiple tape-out experience, AI tool integration
Technologies
Cadence VLE, Cadence VXL, Mentor Calibre
Responsibilities
Design and develop critical analog, mixed-signal, and custom digital blocks; Perform layout verification (LVS/DRC/Antenna); Ensure timely delivery of block-level layouts with acceptable quality; Plan and execute project schedules; Collaborate with global engineering teams
Seniority
Senior, hands-on IC
