Engineer, DEG Layout
Core
Designing and verifying analog, mixed-signal, custom digital, and full-chip layouts for memory and storage solutions.
Role type
Senior IC physical design engineer (analog/mixed-signal/digital)
Builds
Custom digital blocks, standard cells, and full-chip layouts for DRAM, NAND, and NOR memory products
Domain
Semiconductor manufacturing (memory and storage)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
analog layout design, mixed-signal layout design, custom digital block layout, standard cell design, full-chip layout, LVS verification, DRC verification, antenna rule checking, shielding design, matching design, latch-up analysis, electromigration (EM) analysis, IR drop analysis, totem pole checking, quality assurance, documentation, auto placement, routing, skill coding, automation, project planning, area estimation, time estimation, scheduling, delegation, execution, team leadership, sub-block layout review, global engineering team collaboration, AI-driven layout automation
Preferred skills
AI tool integration for layout tasks
Technologies
Auto placement tools, routing tools, LVS/DRC checkers, AI automation frameworks
Responsibilities
Develop digital block layouts using auto placement and route tools; perform layout verification including LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks, and quality checks; support team members in sub-block-level layout execution and review; automate layout execution tasks using AI; present layout project progress to global engineering teams
Seniority
Senior, hands-on IC with leadership responsibilities
