Staff layout Engineer – DPG Layout
Core
Own the development and physical implementation of critical analog, mixed-signal, and custom digital blocks, including block-level and full-chip layout ownership.
Role type
Staff layout engineer (analog/mixed-signal/custom digital)
Builds
Critical analog, mixed-signal, and custom digital blocks for memory and storage solutions
Domain
Semiconductor manufacturing (VLSI/IC design)
Required skills
Analog/custom layout design, Cadence Virtuoso (VLE/VXL), Calibre DRC/LVS, AI-assisted layout workflows, Python/TCL/SKILL scripting, memory array layout (DRAM/SRAM/CAM/OTP), analog fundamentals (matching, EM, latch-up, IR-drop), yield optimization
Preferred skills
None stated
Technologies
Cadence Virtuoso, Calibre, Python, TCL, SKILL
Responsibilities
Lead layout implementation using AI-assisted and automated workflows, perform and automate layout verification activities (DRC, LVS, Antenna, Yield, ESD, TOTEM, EM/IR), drive on-time delivery of blocks with risk prediction, develop AI-enabled methodologies for floorplanning and parasitic estimation, guide and mentor engineers in analog layout fundamentals and automation-first approaches, collaborate with Design, CAD, Verification, Reliability, and Program Management teams, drive continuous improvement by converting manual bottlenecks into scalable automated flows
Seniority
Staff, technical leadership & mentorship
