STAFF Engineer -DEG Layout
Core
Designing and verifying critical analog, mixed-signal, and custom digital blocks at the full chip level for memory and storage solutions.
Role type
Staff IC analog/mixed-signal layout engineer
Builds
Custom digital blocks, analog/mixed-signal circuits (PLL, ADC, DAC, LDO, Bandgap, etc.), and full chip layouts
Domain
Semiconductor manufacturing, memory and storage solutions
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog layout design, mixed-signal layout, custom digital block layout, LVS/DRC verification, AI tool integration for layout automation, project scheduling, team leadership, tape-out support
Preferred skills
Experience with temperature sensors, charge pumps, current mirrors, comparators, differential amplifiers, multiple tape-out support
Technologies
Cadence VLE/VXL, Mentor Graphic Calibre
Responsibilities
Develop layout designs for critical analog and mixed-signal blocks; perform layout verification (LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR); guide team members in sub-block-level layout execution; automate layout tasks using AI tools; lead planning and scheduling for multiple projects; communicate with global engineering teams
Seniority
Staff, hands-on IC with leadership responsibilities
