SENIOR ENG-HIG-HBM-LAYOUT
Core
Designing and integrating analog, mixed-signal, and custom digital blocks for High Bandwidth Memory (HBM) chips used in AI and high-performance computing.
Role type
Senior IC Layout Engineer (HBM)
Builds
HBM memory chips for AI and high-performance computing applications
Domain
Semiconductor manufacturing, Memory technology, Analog/Mixed-Signal IC design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog/custom layout development, Cadence VLE/VXL, Mentor Calibre DRC/LVS, TSV build, Memory build architectures, Physical verification, Project management
Preferred skills
Multiple tape-out support, Team leadership
Technologies
Cadence VLE, Cadence VXL, Mentor Calibre
Responsibilities
Build and develop critical analog, mixed-signal, and custom digital blocks; Build and tapeout PWF Reticles; Collaborate with Scribe Build team on Advanced Packaging; Engage in TSV build with HIG-HBM DTPCO teams; Perform layout verification (LVS/DRC/Antenna checks); Guide less experienced team members in sub-block-level layouts
Seniority
Senior, hands-on IC with team leadership
