Principal Engineer- HIG HBM Layout
Core
Designing and developing complex Application-Specific Integrated Circuits (ASICs) for High Bandwidth Memory (HBM) products serving AI and high-performance computing applications.
Role type
Principal Engineer, Analog/Mixed-Signal IC Layout
Builds
High Bandwidth Memory (HBM) chips for AI and HPC
Domain
Semiconductor / VLSI / Memory
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog and custom layout development, die design, floor planning, manual routing, high-speed interface principles, mixed-signal design, off-chip signaling, architecture analysis and optimization, project management, team leadership and hiring
Preferred skills
Industry standards committee participation, customer support for product implementation, multi-site team collaboration
Technologies
Cadence VLE/VXL, Calibre DRC/LVS
Responsibilities
Lead the establishment and growth of a layout team to meet global HBM requirements, manage tasks and resources for multiple projects, generate and communicate design specifications, assist customers in product implementation, manage team performance and retention
Seniority
Principal, hands-on IC design with team leadership