SoC Physical Verification Engineer, HBM
Core
Lead end-to-end physical verification sign-off for full-chip and hierarchical designs in next-generation HBM logic die and memory-centric SoCs.
Role type
Senior IC physical verification engineer (HBM/SoC)
Builds
Tape-out-ready silicon for advanced-node system-on-chip and heterogeneous integration designs
Domain
Semiconductor manufacturing, advanced-node physical design, Heterogeneous Integration
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
full-chip physical verification, DRC, LVS, ERC, PERC, DFM, reliability verification (ESD, latch-up, electromigration), foundry rule deck management, Python/Tcl/Perl scripting, AI/ML tool adoption
Preferred skills
HBM/DRAM physical verification, multi-die/chiplet/2.5D-3D integration, GPU/CPU high-performance accelerator implementation, post-silicon failure analysis, FEOL/BEOL rule familiarity
Technologies
Calibre, IC Validator (ICV), Pegasus, Python, Tcl, Perl
Responsibilities
Lead end-to-end physical verification sign-off for full-chip and hierarchical designs; Execute and debug foundry-qualified rule decks and manage waivers; Perform reliability verification across power domains; Run density, metal fill, and CMP checks; Perform parasitic RC extraction and support post-silicon correlation; Develop and optimize physical verification flows and automation; Drive adoption of AI/ML-based verification tools; Partner with physical design, EDA, and foundry teams
Seniority
Senior, hands-on IC