New College Grad - HBM Layout Engineer
Core
Designing IC layouts for leaf cells, standard cells, or sub-blocks to ensure design accuracy through physical verification.
Role type
Entry-level IC layout engineer
Builds
Physical layouts for memory and storage chips
Domain
Semiconductor manufacturing / IC physical design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Electronic circuit concepts, circuit simulation tools, DRC/LVS interpretation, project planning, layout trade-off analysis
Preferred skills
Pre-silicon circuit design, analog circuits, MOS concepts, semiconductor fabrication, scripting (C++, Python), Cadence VLE/VXL, Mentor Graphics Calibre
Technologies
Cadence VLE/VXL, Mentor Graphics Calibre
Responsibilities
Design layout for leaf cells, standard cells, or sub-blocks; Apply systematic approach to IC layout design; Interpret DRC/LVS and physical verification checks; Plan work to meet project timelines; Collaborate with internal teams for project execution
Seniority
Junior, new graduate