Sr AMS Layout Engineer-DPG-LPDDR
Core
Custom analog and mixed-signal layout for critical blocks in LPDDR PHYs, including datapath, bias networks, IO analog frontends, and high-speed interfaces.
Role type
Senior IC analog/mixed-signal layout engineer (LPDDR PHY)
Builds
High-performance LPDDR memory products for data centers, mobile, and edge computing
Domain
Semiconductor memory (DRAM) / High-speed analog and mixed-signal design
Deliverable
production ML models | product features
Required skills
Analog and mixed-signal layout, high-speed serial link design (LPDDRx), signal integrity management (skew, impedance, crosstalk), array-based layout optimization, custom digital block layout, layout-aware co-design, DRC/LVS closure, parasitic extraction, power distribution and grounding strategies, JEDEC compliance, PPA optimization
Preferred skills
AI/ML knowledge for layout automation and data-driven optimization
Technologies
VXL, advanced process nodes, LPDDR PHY architectures
Responsibilities
Own custom analog and mixed-signal layout of critical analog blocks for LPDDR PHYs; Execute high-speed LPDDR interface layout addressing signal integrity challenges; Design and optimize array-based layouts for LPDDR DQ/DQS byte lanes and CA lanes; Implement custom digital block layouts within the LPDDR PHY; Drive layout-aware co-design with circuit designers; Perform DRC/LVS closure, parasitic extraction reviews, and correlation with simulation results; Support post-layout optimization and ECOs; Collaborate with architecture, circuit, verification, and silicon debug teams; Contribute to PPA optimization with a focus on low-power operation and area efficiency
Seniority
Senior, hands-on IC