Staff AMS Layout engineer-DPG-LPDDR
Core
Lead custom analog and mixed-signal layout for critical LPDDR PHY blocks, ensuring robust operation, signal integrity, and PPA optimization in advanced technology nodes.
Role type
Staff AMS Layout Engineer (LPDDR/High-Speed Interfaces)
Builds
High-performance LPDDR memory chips for data centers, mobile, and edge computing
Domain
Semiconductor manufacturing, Memory (DRAM), High-Speed Digital/Analog Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Custom analog and mixed-signal layout design, High-speed interface design (LPDDR/LPDDRx), Signal integrity analysis (skew, impedance, crosstalk, jitter), Array-based layout architecture, Physical verification (DRC/LVS/PEX), PPA optimization, Scripting (SKILL/Python/TCL), Mentorship
Preferred skills
AI/ML concepts for layout automation, VXL-compatible flows
Technologies
SKILL, Python, TCL, VXL, LPDDR, DRC, LVS, PEX
Responsibilities
Own and drive custom analog and mixed-signal layout for critical LPDDR PHY blocks, Lead high-speed LPDDR interface layout execution solving signal integrity challenges, Architect scalable array-based layout strategies for DQ/DQS and CA lanes, Drive integration of custom digital and mixed-signal blocks within the PHY, Establish robust power distribution, grounding, and isolation strategies, Own physical verification and signoff closure including DRC/LVS and parasitic extraction, Drive post-layout optimization and ECOs for yield and manufacturability, Mentor engineers and contribute to layout methodologies and best practices
Seniority
Staff, hands-on IC with mentorship responsibilities