Senior Engineer, CAD
Core
Evaluating, improving, and debugging Electronic Design Automation (EDA) tools and flows for the physical layout, verification, and design of CMOS integrated circuits to increase layout team productivity.
Role type
Senior IC CAD Engineer (Layout Automation & EDA)
Builds
Automated layout flows, AI-assisted placement/routing workflows, and verification methodologies for memory chips.
Domain
Semiconductor manufacturing / Physical Design / EDA
Deliverable
production ML models | product features
Required skills
Layout automation, Physical Verification (DRC/ERC/LVS/DFM), Place and Router flows, CMOS process knowledge, Scripting (Skill, Perl, Python, Tcl), Linux, AI-driven automation methodologies
Preferred skills
PDN analysis (Totem/VoltusXFA/XA), EMIR/RC-Extraction/ESD/Latch-up expertise, Mentorship
Technologies
Cadence Virtuoso, Synopsys Custom Compiler, Pulsic Unity, Itools, Totem, VoltusXFA, XA, Calibre, ICV
Responsibilities
Solve daily challenges for memory layout teams, develop methodologies for reliable layout with faster Time to Market, lead layout flows implementation using AI-assisted and automated workflows, continuously evaluate and implement new tools to improve layout development flows, provide guidance and mentorship to junior team members, develop and deploy AI-enabled methodologies for semi-automated floorplanning and parasitic estimation
Seniority
Senior, hands-on IC
