Senior Engineer, CAD
Core
Senior IC engineer specializing in layout automation and EDA tool debugging for CMOS integrated circuits.
Role type
Senior IC machine-learning engineer (layout automation)
Builds
AI-assisted and automated workflows for memory layout, placement, routing, and optimization
Domain
Semiconductor manufacturing / Physical Design / Electronic Design Automation
Deliverable
production ML models
Required skills
Layout automation, Physical Verification, EDA tool customization, AI-driven automation, Place and Router flows, PDN analysis, DRC/ERC/LVS/DFM debugging, CMOS process knowledge, Linux, Python, Perl, Tcl, Skill
Preferred skills
AI-enabled methodologies for floorplanning and parasitic estimation
Technologies
Cadence Virtuoso, Synopsys Custom Compiler, Pulsic Unity, Itools, Totem, VoltusXFA, XA, Calibre, ICV
Responsibilities
Evaluate and improve EDA tools and flows for physical layout and verification; Develop methodologies for reliable layout with faster Time to Market; Lead layout flows implementation using AI-assisted and automated workflows; Provide guidance and mentorship to junior team members
Seniority
Senior, hands-on IC