Director, HBM RTL Design and Integration
Core
Lead a team in the design, integration, and delivery of next-generation HBM SoC logic die, focusing on RTL development and IP integration for AI/ML and high-performance computing systems.
Role type
Director, HBM RTL Design and Integration
Builds
Next-generation HBM SoC logic die
Domain
Semiconductor / Memory / High-Performance Computing
Deliverable
production ML models
Required skills
SoC RTL design, SoC integration, IP integration (controllers, NOC, microcontrollers, PHY-adjacent logic, RAS, MBIST), EDA tools, scripting (SystemVerilog, Python, TCL), DRAM/HBM systems knowledge, JEDEC standards
Preferred skills
Tape-out leadership, cross-functional SoC program management, global engineering team management
Technologies
SystemVerilog, Python, TCL, TSMC process nodes
Responsibilities
Lead SoC RTL design and integration including subsystem partitioning and IP integration; Drive translation of architectural specifications into RTL implementations; Oversee SoC integration aspects like clocking, reset, and power intent; Establish design methodologies and best practices; Partner with Architecture, Verification, Physical Design, Firmware, and Product Engineering teams; Build, lead, and scale a high-performing RTL design and integration team.
Seniority
Director, technical leadership & team management
