Principal Engineer- HIG HBM Layout
Core
Lead end-to-end layout execution and full-chip technical decisions for analog, mixed-signal, and custom digital blocks in HBM products.
Role type
Principal Engineer, HBM Layout
Builds
High Bandwidth Memory (HBM) chips with analog/mixed-signal and custom digital blocks
Domain
Semiconductor / Memory / VLSI Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog/mixed-signal layout design, Array Layout, Decoder, Control logic, IOs, PLLs, ADCs, DACs, LDOs, Bandgaps, Reference Generators, Charge Pumps, Current Mirrors, Comparators, Differential Amplifiers, Floor planning, Manual routing, Cadence VLE/VXL, Calibre DRC/LVS, Project planning, Team leadership, Tape-out management
Preferred skills
AI/automation adoption for layout productivity, Cross-functional collaboration, Industry engagement
Technologies
Cadence VLE/VXL, Calibre DRC/LVS
Responsibilities
Lead end-to-end layout execution for analog, mixed-signal, and custom digital blocks; Own full-chip technical decisions covering analog, digital, memory, ESD, EM/IR; Perform and oversee layout verification activities including LVS, DRC, and Antenna checks; Lead and mentor the layout team; Drive innovation and productivity improvements through AI/automation; Collaborate with global cross-functional teams; Support customer and product integration needs; Contribute to organizational growth and leadership initiatives
Seniority
Principal, hands-on IC with team leadership
