Analog/Mixed Signal ASIC Design Engineer
Core
Design high-speed, high-performance, low-power mixed-signal IPs (SerDes, DDR, PLL, DAC, ADC, sensors) for 5G, AI/ML, compute, and automotive applications.
Role type
Senior IC analog/mixed-signal ASIC design engineer
Builds
Mixed-signal IP blocks for Qualcomm products
Domain
Semiconductors / Analog Mixed Signal
Deliverable
production ML models | product features
Required skills
Schematic capture, Cadence Virtuoso, analog circuit design, architecture definition, analog/digital design partitioning, silicon bringup, debugging
Preferred skills
High-speed analog design (CTLE, CDR, PLL RXAFE), Matlab, Python, design for yield, sampled domain signal processing
Technologies
Cadence Virtuoso, SPICE, MATLAB, Verilog, VHDL
Responsibilities
Schematic capture and simulations, participate in architecture definition and analog/digital design partitioning, work with cross-functional teams (layout, digital), work with testing team for silicon bringup and debugging
Seniority
Senior, hands-on IC
