Analog/Mixed Signal ASIC Design Engineer
Core
Design high-performance, low-power mixed-signal IPs (SerDes, DDR, PLL, DAC, ADC, sensors) for Qualcomm's SOCs and RF transceivers targeting 5G, AI/ML, compute, and automotive applications.
Role type
Senior IC analog/mixed-signal ASIC design engineer
Builds
Mixed-signal IP blocks for System-on-Chip (SoC) integration
Domain
Semiconductor / Analog Mixed Signal Design
Required skills
Analog circuit design, Mixed-signal IP design, Schematic capture, Circuit simulation, Cadence Virtuoso, ASIC design, Nanometer planar CMOS/FinFET process knowledge
Preferred skills
Matlab, Python, Signals and Systems, Sampled Domain signal processing, Design for yield, Production challenges
Technologies
Cadence Virtuoso, SPICE, MATLAB, Verilog, VHDL
Responsibilities
Define architecture and perform analog/digital design partitioning, Create schematics and run circuit simulations, Collaborate with layout and digital teams for implementation and verification, Support post-silicon verification, bringup, debug, and production
Seniority
Senior, hands-on IC
