Logic Digital Verification Engineer
Core
Building and maintaining a complex verification environment for a self-powered IoT computing element (RF energy harvesting sticker) to ensure quality across block-level and full-chip designs.
Role type
Senior IC digital verification engineer (SoC/ASIC)
Builds
Production verification environments and test plans for mixed-signal SoCs
Domain
Semiconductor / IoT / Hardware verification
Required skills
SystemVerilog/UVM, RTL design, SoC verification, mixed-signal simulation, HW/SW co-simulation, Python scripting, Unix/Linux, digital ASIC design flows
Preferred skills
Low power techniques (UPF), mixed-signal SoCs, SW/HW co-development
Technologies
Verilog, MATLAB, UVM, SV, Python, Linux
Responsibilities
Define and implement robust SV/UVM verification solutions including test benches and methodologies; Integrate mixed-signal SoC simulation environments; Collaborate with Digital, Analog, Software, and Back-end teams to define functional, power, and performance goals.
Seniority
Mid-level, hands-on IC
