Senior Hardware Design Engineer
Core
Lead hardware design for Intel's Ethernet Infrastructure Processing Unit (IPU) and Foundation NIC (FNIC) product lines, focusing on high-speed I/O protocols like PCIeGen6-7, DDR5-6, and PAM4 Ethernet 224Gb.
Role type
Senior Hardware Design Engineer (High-Speed I/O & System)
Builds
Ethernet networking products for cloud service and telecommunications data centers
Domain
Semiconductor / High-Speed Data Communications
Required skills
High-speed PCB design (Analog/Digital), Signal Integrity (SI) & Power Integrity (PI), Transmission line theory, FPGA development, Verilog coding, Root cause debugging, Lab test equipment operation (Oscilloscopes, VNA, TDR, BERT), Component selection management
Preferred skills
AI-based tools experience, C++/Python/MATLAB programming
Technologies
PCIeGen6-7, DDR5-6, PAM4 Ethernet 224Gb, FPGA, Verilog, C++, Python, MATLAB, Oscilloscopes, VNA, TDR, BERT
Responsibilities
Develop board designs from schematic through silicon power-on enablement and debug; Provide technical leadership to resolve hardware, schematic, layout, and DFx issues; Identify and qualify new hardware solutions; Manage part/component selection; Interface with design, system, and pre/post-silicon teams.
Seniority
Senior, hands-on IC
