DFT Design Engineer
Core
Design and implement DFT solutions including scan architecture, ATPG, and memory BIST/repair for semiconductor chips.
Role type
DFT Design Engineer
Builds
DFT circuitry and verification environments for silicon chips
Domain
Semiconductor / Digital Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Spyglass DFT, Scan Architecture (SSN Topology), ATPG, fault models, JTAG implementation, Memory BIST, Memory Repair (BIRA/BISR), Gate Level Simulation, timing annotations, RTL coding, shell scripting, DRC debugging, ATE debugging
Preferred skills
Post-Silicon/manufacturing team collaboration
Technologies
Spyglass, industry standard DFT tools
Responsibilities
Implement JTAG, Memory BIST, and Memory Repair circuitry; Perform DFT verification using Gate Level Simulations with timing annotations; Solve DFT problems, simulation failures, ATPG coverage improvements, and DRC debug; Collaborate with post-Silicon/manufacturing teams on ATE debugging and issue resolution
Seniority
Mid-level, hands-on IC
