Mid-level Physical Design Engineer CPU
Core
Execute physical design implementation for CPU core blocks or subsystems within the RTL-to-GDS flow, contributing to high-performance, power-efficient silicon.
Role type
Mid-level IC physical design engineer (CPU)
Builds
CPU cores and subsystems for client, server, IoT, and AI platforms
Domain
Semiconductor / CPU Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Logic synthesis, place and route (PnR), static timing analysis (STA), power analysis, physical verification (DRC/LVS), design closure, scripting (TCL, Python/Perl/Ruby), cross-functional collaboration
Preferred skills
CPU micro-architecture knowledge, floor-planning, clock distribution, noise analysis, reliability verification, RTL to GDS methodologies, Synopsys/Cadence tool suites
Technologies
Synopsys (Fusion Compiler, ICC2, PrimeTime), Cadence (genus, innovus), TCL, Python, Perl, Ruby
Responsibilities
Execute physical design implementation for CPU core blocks; Perform synthesis, floor planning, place and route, and design closure; Conduct static timing analysis, power analysis, and physical verification; Identify and debug timing, power, and design rule violations; Develop and maintain design automation scripts; Collaborate with RTL, verification, and full-chip teams; Document technical work and share knowledge.
Seniority
Mid-level, hands-on IC