Sr. Engineer, RTL Implementation
Core
Iterating front-end CAD flows on multiple process technologies to refine CPU core configurations and optimize Power, Performance, and Area (PPA) for a RISC-V based CPU.
Role type
Senior RTL Implementation Engineer (CPU Physical Design)
Builds
High-performance RISC-V CPU cores
Domain
Semiconductor / CPU Design / RISC-V
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
High-performance physical design, RTL coding (Verilog/VHDL), synthesis, place and route tools, physical design methodology, CPU micro-architecture
Preferred skills
Industry-standard tools for simulation and power analysis, innovative techniques for PPA optimization
Technologies
RISC-V, Verilog, VHDL
Responsibilities
Perform synthesis and initial place and route for new and legacy designs, Collaborate with core micro-architects to optimize core configurations, Optimize power, performance, and area through physical design experiments, Enhance physical design environment, tools, and methodologies
Seniority
Senior, hands-on IC
