Principal SoC Signoff Engineer
Core
Lead timing-constraint development and signoff for complex SoCs, digital/AMS/SerDes IPs, and critical interfaces across functional and test modes.
Role type
Principal SoC Signoff Engineer (IC Timing)
Builds
Custom integrated circuits (ICs) and complex IPs for semiconductor customers
Domain
Semiconductor manufacturing, SoC design, Static Timing Analysis (STA)
Required skills
STA constraint development, STA signoff margining, UPF, SDC, MV/DVFS methodologies, EDA tool proficiency, technical mentorship, process definition
Preferred skills
Custom silicon delivery, team scaling, agentic AI workflows, Synopsys EDA suite expertise
Technologies
Synopsys, Cadence, Siemens EDA, UPF, SDC
Responsibilities
Lead timing-constraint development for complex SoCs and IPs; Define signoff margins for ASIC implementation and STA; Establish processes for MV/DVFS STA signoff; Provide technical mentorship to engineering teams; Champion AI/ML-enabled STA methodologies
Seniority
Principal, hands-on IC with strategy & mentorship
