Staff STA Engineer
Core
Owning full chip and block level timing closure throughout the entire project cycle for complex multi-instantiated SoCs.
Role type
Staff STA Engineer
Builds
Modern silicon chips using 3nm and advanced SoC 2.5D/3D technology
Domain
Semiconductor / Silicon Engineering
Deliverable
production ML models
Required skills
Static Timing Analysis (STA), Timing closure, Multi-power domain design, Timing corners/modes (DFT, process variations, signal integrity), Automation (Perl/Tcl/Python), 5nm/3nm technology experience
Preferred skills
Electrical Engineering (Masters), Synthesis, Logic Equivalence, DFT, CLP, Backend methodology
Technologies
3nm, 5nm, 2.5D, 3D, DFT, Perl, Python, TCL
Responsibilities
Owning full chip and block level timing closure, Handling timing constraints for functional and test mode, Resolving sophisticated timing issues for major building blocks, ECO generation at block and top level, Collaborating with silicon engineering groups and EDA vendors
Seniority
Staff, hands-on IC