Principal Physical Design
Core
Lead physical design implementation and signoff methodologies for advanced DRAM digital designs from RTL through tapeout, focusing on timing closure, power integrity, and design reliability.
Role type
Principal Physical Design Engineer (DRAM/ASIC)
Builds
Next-generation memory products (DRAM)
Domain
Semiconductor / Memory / Physical Design
Required skills
Physical design implementation (floorplanning, place and route, CTS, timing closure), Power integrity (PDN, IR drop, EM), Signoff methodologies, Scripting (Python, Tcl), Advanced process technologies
Preferred skills
Methodology innovation for large-scale ASIC/SoC, AI-assisted engineering tools, Technical leadership and mentoring
Technologies
Synopsys IC Compiler II, Fusion Compiler, PrimeTime, PrimePower, RedHawk
Responsibilities
Lead physical design implementation including floorplanning, place and route, clock tree synthesis, and tapeout; Drive power integrity strategies and signoff (PDN, IR drop, EM); Collaborate to resolve timing, congestion, and signal integrity challenges; Develop automation solutions and methodology improvements; Mentor engineers and influence future product roadmaps
Seniority
Principal, hands-on IC with technical leadership
