DFT Engineer ( Testchip Architecture/ RTL DFT)
Core
Lead DFT architecture and methodology development for complex test-chip designs, defining Scan, MBIST, ATPG, and supporting post-silicon debug activities.
Role type
Senior IC DFT Engineer (Testchip Architecture/RTL DFT)
Builds
Test architectures including Scan, Mem-BIST, ATPG for test-chip designs
Domain
Semiconductor manufacturing / Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
JTAG, Scan, Memory BIST, ATPG, SystemVerilog, UVM, Tcl, Python, Shell scripting, ATE pattern handling, gate-level simulation
Preferred skills
RTL development, functional verification of logic circuits
Technologies
Tessent, SystemVerilog, UVM, Tcl, Python, Shell
Responsibilities
Lead DFT architecture for test-chip designs; Develop and maintain DFT methodologies; Own and deliver test architectures including Scan, Mem-BIST, ATPG; Provide post-silicon support; Collaborate with cross-functional design, verification, and physical design teams
Seniority
Senior, hands-on IC
