Principal STA Engineer
Core
Technical authority for signoff timing convergence and shift-left strategies within the Physical Design organization for SoC closure.
Role type
Principal STA Engineer (Physical Design)
Builds
SoC-level designs with predictable timing closure and high-quality signoff.
Domain
Semiconductor manufacturing / Physical Design / Static Timing Analysis
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SoC-level MCMM STA, physically aware ECO generation, GLS enablement, advanced process node analysis, DFT timing modes, IP integration, flow automation scripting (TCL/Python/Perl), data-driven process improvement, reuse methodologies
Preferred skills
Custom silicon delivery for automotive/HPC/AI, adoption of new tools and flows, design-reuse best practices
Technologies
TCL, Python, Perl, MCMM, GLS, ECO
Responsibilities
Own SoC-level signoff STA including timing ECO delivery and GLS enablement; Drive robust co-optimization strategies to achieve benchmark PPAS targets; Develop and maintain PPAS/status dashboards using scripting automation; Collaborate with RTL, Verification, Physical Design, and DFT teams for design convergence; Rationalize timing margins; Analyze design metrics to propose process improvements; Automate and enhance STA flows using scripting
Seniority
Principal, technical authority & strategy
